Charge-Mode Parallel Architecture for Matrix-Vector Multiplication

An internally analog, e x t e d y digital architecture for matrix-vector multiplication is presented. Fully parallel processing allows for high data throughput and minimal latency. The analog architecture incorporates an array of chargemode analog computational cells with dynamic storage and mwparallel fiash analog-to-digital converters (ADC). Each of the cells includes a dynamic storage element and a charge injection device computing binary inner product of two arguments. The matrix elements are stored in the array of computational cells in bit-parallel fashion, and the input vector is presented bit-serially. Digital post-processing is then performed on the ADC outputs to construct the resulting product with precision higher than that of each conversion. The analog architecture is tailored for highdensity and low power VLSI implementation, and matrix dimensions of 128 x 512 and ADC resolution of 6 bits for an overall resolution in excess of 8 bits are feasible on a 3 mm x 3 mm chip in standard CMOS 0.5 pm technology.